| Item |
Specification |
| CPU: |
- Upward-compatible with the H8/300 CPU at the object-code level
- General-register machine
- Sixteen 16-bit general registers(also usable as sixteen 8-bit registers, eight 16-bit registers, or eight 32-bit registers)
- High-speed operation
- Maximum clock rate: 25 MHz
- Add/subtract: 80 ns
- Multiply/divide: 560 ns
- 16-Mbyte address spaceInstruction features
- 8/16/32-bit data transfer, arithmetic, and logic instructions
- Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
- Signed and unsigned divide instructions (16 bits ÷ 8bits, 32 bits ÷ 16 bits)
- Bit accumulator function
- Bit manipulation instructions with register-indirect specification of bit positions
|
| Memory: |
- H8/3069F
- ROM: 512 kbytes
- RAM: 16 kbytes
|
| Interrupt controller: |
- Seven external interrupt pins: NMI, IRQ0 to IRQ5
- 36 internal interrupts
- Three selectable interrupt priority levels
|
| Bus controller: |
- Address space can be partitioned into eight areas, with independent bus specifications in each area
- Chip select output available for areas 0 to 7
- 8-bit access or 16-bit access selectable for each area
- Two-state or three-state access selectable for each area
- Selection of two wait modes
- Number of program wait states selectable for each area
- Direct connection of burst ROM
- Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used as interval timer)
- Bus arbitration function
|
| DMA controller (DMAC): |
- Short address mode
- Maximum four channels available
- Selection of I/O mode, idle mode, or repeat mode
- Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts linterrupts from the SCI, or external requests
- Full address mode
- Maximum two channels available
- Selection of normal mode or block transfer mode
- Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, external requests, or auto-request
|
| 16-bit timer, 3 channels: |
- Three 16-bit timer channels,capable of processing up to six pulse outputs or six pulse inputs
- 16-bit timer counter (channels 0 to 2)
- Two multiplexed output compare/input capture pins (channels 0 to 2)
- Operation can be synchronized (channels 0 to 2)
- PWM mode available (channels 0 to 2)
- Phase counting mode available (channel 2)
- DMAC can be activated by compare match/input capture A interrupts (channels 0 to 2)
|
| 8-bit timer, 4 channels: |
- 8-bit up-counter (external event count capability)
- Two time constant registers
- Two channels can be connected
|
| Programmable timing pattern controller (TPC): |
- Maximum 16-bit pulse output,using 16-bit timer as time base
- Up to four 4-bit pulse output groups (or one 16-bit group,or two 8-bit groups)
- Non-overlap mode available
- Output data can be transferred by DMAC
|
| Watchdog timer (WDT),1 channel: |
- Reset signal can be generated by overflow
- Usable as an interval timer
|
| Serial communication interface (SCI), 3 channels: |
- Selection of asynchronous or synchronous mode
- Full duplex: can transmit and receive simultaneously
- On-chip baud-rate generator
- Smart card interface functions added
|
| A/D converter: |
- Resolution: 10 bits
- Eight channels, with selection of single or scan mode
- Variable analog conversion voltage range
- Sample-and-hold function
- A/D conversion can be started by an external trigger or 8-bit timer compare-match
- DMAC can be activated by an A/D conversion end interrupt
|
| D/A converter: |
- Resolution: 8 bits
- Two channels
- D/A outputs can be sustained in software standby mode
|
| I/O ports: |
- 70 input/output pins
- 9 input-only pins
|
| Operating modes: |
- Six MCU operating modes
| Mode |
Address Space |
Address Pins |
Initial Bus Width |
Max. Bus Width |
| Mode1 |
1 Mbyte |
A19 to A0 |
8 bits |
16 bits |
| Mode2 |
1 Mbyte |
A19 to A0 |
16 bits |
16 bits |
| Mode3 |
16 Mbytes |
A23 to A0 |
8 bits |
16 bits |
| Mode4 |
16 Mbytes |
A23 to A0 |
16 bits |
16 bits |
| Mode5 |
16 Mbytes |
A23 to A0 |
8 bits |
16 bits |
| Mode7 |
1 Mbyte |
- |
- |
- |
On-chip ROM is disabled in modes 1 to 4
|
| Power-down state: |
- Sleep mode
- Software standby mode
- Hardware standby mode
- Module standby function
- Programmable system clock frequency division
|
| Other features: |
- On-chip clock pulse generator
|
